1. Technical Field
The present invention relates to power conversion devices that convert direct current voltage to alternating current voltage, and in particular, to such devices that reduce loss in a single phase three-level power conversion device.
2. Related Art
With a view to reducing waveform distortion in an inverter device that converts direct current power to alternating current power, a three-level inverter type has been proposed (see, for example, Japanese Patent Publication Nos. JP-A-2008-178284 and JP-A-2007-28860). Hereafter, the configurations and actions of circuits disclosed in Japanese Patent Publication Nos. JP-A-2008-178284 and JP-A-2007-28860 will be described with reference to FIGS. 9 to 11 as heretofore known examples of a single phase three-level inverter.
FIG. 9 is a circuit configuration diagram of the single phase three-level inverter disclosed in JP-A-2008-178284. The single phase three-level inverter, with a controller (CN) 6a controlling an on-off condition of switch elements configuring an inverter circuit (IC) 3a, converts a direct current voltage 2E of a power source 1 into a single phase alternating current voltage, and supplies the single phase alternating current voltage to a load 5.
In FIG. 9, a capacitor C1 and capacitor C2 are connected in series to either end of a power source 1. The capacitor C1 and capacitor C2 configure a first direct current power source and second direct current power source. When the voltage of the power source 1 is 2E, the voltages of the capacitor C1 and capacitor C2 are each E. Also, a voltage detector (VD) 2 is connected to both ends of the power source 1, and the voltage 2E of the power source 1 is detected by the voltage detector 2.
Next, a series circuit in which switch elements 1u to 4u are connected in series is connected to both ends of a series circuit formed of the capacitor C1 and capacitor C2. Diodes 1x to 4x are respectively connected in inverse parallel to the switch elements 1u to 4u configuring the series circuit. Also, diodes 5x and 6x are connected in series between the connection point of the switch elements 1u and 2u and the connection point of the switch elements 3u and 4u. Furthermore, the connection point of the diodes 5x and 6x is connected to a connection point of the capacitors C1 and C2.
Also, a series circuit in which switch elements 1v to 4v are connected in series is connected to both ends of the series circuit formed of the capacitor C1 and capacitor C2. Diodes 1y to 4y are respectively connected in inverse parallel to the switch elements 1v to 4v configuring the series circuit. Also, diodes 5y and 6y are connected in series between the connection point of the switch elements 1v and 2v and the connection point of the switch elements 3v and 4v. Furthermore, the connection point of the diodes 5y and 6y is connected to a connection point of the capacitors C1 and C2.
Herein, the switch elements 1u to 4u and diodes 1x to 6x configure a first half bridge. The switch elements 1v to 4v and diodes 1y to 6y configure a second half bridge. Furthermore, the first half bridge and second half bridge configure the inverter circuit 3a. 
The connection point of the switch elements 2u and 3u is a U terminal, and the connection point of the switch elements 2v and 3v is a V terminal. The U terminal and V terminal are alternating current output terminals of the inverter circuit 3a. A voltage detector (VD) 4 and the load 5 are connected in parallel between the U terminal and V terminal.
Next, the controller 6a outputs gate signals of the switch elements 1u to 4u and 1v to 4v. In order to do this, the controller 6a includes an output voltage command unit 61, a control computation unit 62, and a first PWM controller 63a. 
Hereafter, a description will be given of actions of the controller 6a. Firstly, the output voltage command unit 61 outputs the command value of a voltage to be applied by the inverter circuit 3a to the load.
The control computation unit 62 carries out an AVR computation with a PI regulator, or the like, so that an alternating current output voltage detected by the voltage detector 4 and the output voltage command output by the output voltage command unit 61 match. Furthermore, the control computation unit 62 computes a modulation signal for a PWM control by dividing the result of the AVR computation by a direct current input voltage detected by the voltage detector 2.
The first PWM controller 63a carries out a size comparison of an internally generated carrier signal and the modulation signal output by the control computation unit 62, and generates the gate signals of the switch elements 1u to 4u and 1v to 4v. The gate signals are output to the inverter circuit 3a. 
The switch elements 1u to 4u and 1v to 4v are on-off controlled by the gate signals. As a result of this, a desired alternating current voltage is output between the U and V terminals of the inverter circuit 3a. 
FIG. 10 is a diagram showing an example of an output voltage waveform generated between the U and V terminals of the inverter circuit 3a shown in FIG. 9. As a single phase three-level inverter generally acts on a carrier frequency in the region of 10 kHz, the output voltage has a waveform more nearly sinusoidal.
Table 1 is a table showing voltages output between the U and V terminals of the inverter circuit 3a corresponding to combinations of on-off conditions of the switch elements 1u to 4u and 1v to 4v. By repeating mode 1 to mode 8 shown in Table 1, a voltage with the waveform shown in FIG. 10 is output between the U and V terminals of the inverter circuit 3a. As shown in FIG. 10 and Table 1, the output voltage of the inverter circuit 3a is of five levels, 0, E, 2E, −E, and −2E.
TABLE 1VoltageFirst Half BridgeSecond Half BridgeBetween UU TerminalV Terminaland V1u2u3u4uVoltage1v2v3v4vVoltageTerminalsMode 1OnOnOffOffEOnOnOffOffE0Mode 2OnOnOffOffEOffOnOnOff0EMode 3OnOnOffOffEOffOffOnOn−E2EMode 4OffOnOnOff0OffOffOnOn−EEMode 5OffOffOnOn−EOffOffOnOn−E0Mode 6OffOffOnOn−EOffOnOnOff0−EMode 7OffOffOnOn−EOnOnOffOffE−2EMode 8OffOnOnOff0OnOnOffOffE−E
FIG. 11 is a circuit configuration diagram of the single phase three-level inverter disclosed in Japanese Patent Publication No. JP-A-2007-28860. The single phase three-level inverter of FIG. 11, with a controller (CN) 6b controlling an on-off condition of switch elements configuring an inverter circuit (IC) 3b, converts a direct current voltage 2E of a power source 1 into a single phase alternating current voltage, and supplies the single phase alternating current voltage to a load 5.
A power source 1, and a first direct current power source and second direct current power source formed of capacitors C1 and C2, are the same as in the heretofore known example shown in FIG. 9. A voltage detector 2 is connected to both ends of the power source 1, and a voltage 2E of the power source 1 is detected by the voltage detector 2.
Next, switch elements 1u and 4u are connected in series to both ends of a series circuit formed of the capacitor C1 and capacitor C2, and a circuit in which switch elements 2u and 3u having reverse withstand voltage are connected in inverse parallel is connected between a connection point of the switch elements 1u and 4u and a connection point of the capacitors C1 and C2. Diodes 1x and 4x are connected in inverse parallel to the switch elements 1u and 4u respectively.
Also, switch elements 1v and 4v are connected in series to both ends of a series circuit formed of the capacitor C1 and capacitor C2, and a circuit in which switch elements 2v and 3v having reverse withstand voltage are connected in inverse parallel is connected between a connection point of the switch elements 1v and 4v and a connection point of the capacitors C1 and C2. Diodes 1y and 4y are connected in inverse parallel to the switch elements 1v and 4v respectively.
Herein, the switch elements 1u to 4u and diodes 1x and 4x configure a first half bridge. Also, the switch elements 1v to 4v and diodes 1y and 4y configure a second half bridge. Furthermore, the first half bridge and second half bridge configure the inverter circuit 3b. 
The connection point of the switch elements 1u and 4u is a U terminal, and the connection point of the switch elements 1v and 4v is a V terminal. The U terminal and V terminal are alternating current output terminals of the inverter circuit 3b. A voltage detector 4 and the load 5 are connected in parallel between the U terminal and V terminal.
Next, the controller 6b outputs gate signals of the switch elements 1u to 4u and 1v to 4v. In order to do this, the controller 6b includes an output voltage command unit 61, a control computation unit 62, and a first PWM controller 63b. 
Hereafter, a description will be given of actions of the controller 6b. Of the components of the controller 6b, the output voltage command unit 61 and control computation unit 62 are the same as in the single phase three-level inverter shown in FIG. 9.
The first PWM controller 63b carries out a size comparison of an internally generated carrier signal and a modulation signal output by the control computation unit 62, and generates the gate signals of the switch elements 1u to 4u and 1v to 4v. The on-off conditions of the switch elements 1u to 4u and 1v to 4v are controlled by the gate signals, and a desired alternating current voltage is output between the U and V terminals of the inverter circuit 3b. 
Table 2 is a table showing voltages output between the U and V terminals of the inverter circuit 3b corresponding to combinations of the on-off conditions of the switch elements 1u to 4u and 1v to 4v configuring the inverter circuit 3b. By repeating mode 1 to mode 8 shown in Table 2, a voltage with a waveform the same as the waveform shown in FIG. 10 is output between the U and V terminals of the inverter circuit 3b. As shown in FIG. 10 and Table 2, the output voltage of the inverter circuit 3b shown in FIG. 11 is also of five levels, 0, E, 2E, −E, and −2E.
TABLE 2VoltageFirst Half BridgeSecond Half BridgeBetween UU TerminalV Terminaland V1u2u3u4uVoltage1v2v3v4vVoltageTerminalsMode 1OffOnOnOff0OffOnOnOff00Mode 2OffOnOnOff0OffOffOnOn−EEMode 3OnOnOffOffEOffOffOnOn−E2EMode 4OnOnOffOffEOffOnOnOff0EMode 5OffOnOnOff0OffOnOnOff00Mode 6OffOffOnOn−EOffOnOnOff0−EMode 7OffOffOnOn−EOnOnOffOffE−2EMode 8OffOnOnOff0OnOnOffOffE−E
However, in the heretofore known examples, the single phase three-level inverter carries out a switching action in full bridge mode regardless of the size of the alternating current output voltage. That is, as shown in Table 1 and Table 2, all the switch elements (1u to 4u and 1v to 4v) configuring the first half bridge and second half bridge alternate on and off conditions. Because of this, there is a problem in that conduction loss and switching loss occur in all the switch elements, and conduction loss and reverse recovery loss occur in all the diodes.